Advanced Encryption Standard (AES)
In a joint project with Rockwell Collins, Galois worked to design an FPGA implementation of AES for RC's High-Speed Encryptor (HSE) project. From the final report:
"A team of developers from Rockwell Collins, Inc. and Galois, Inc. successfully produced high-speed embedded Cryptographic Equipment Applications (CEAs), automatically generated from high-level specifications. An algorithm core generated from a Cryptol specification for AES-256 and running in Electronic Codebook mode demonstrated throughput in excess of 16 Gbps. The “crypto waveform” logic uses the Model-Based Development language Simulink. These high-speed CEA implementations comprise a mixture of software code and VHDL, and target a compact new embedded platform designed by Rockwell Collins. Notably, almost no traditional low-level interface code was required in order to implement these high-performance CEAs. In addition, automated formal methods prove that algorithm implementations faithfully implement their high-level specifications. When feedback from the output stage to the input was introduced, thereby defeating the advantage gained by “unrolling” AES rounds, encryption performance for AES-256 still exceeded 1 Gbps, while consuming less than 2% of the available programmable logic for the algorithm core. Significantly, the Rockwell Collins/Galois team was able to design, implement, simulate, integrate, analyze, and test a complex CEA on the new hardware, including AES-256 and Galois Counter Mode (GCM), in less than 3 months."
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